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Last deposits
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Diamante-Simone Crescenzo, Rafael Carrera Rodriguez, Riccardo Alidori, Florent Bruguier, Emanuele Valea, et al.. Hardware accelerator for FIPS 202 hash functions in post-quantum ready SoCs. IOLTS 2024 - IEEE 30th International Symposium on On-Line Testing and Robust System Design, Jul 2024, Rennes, France. ⟨10.1109/IOLTS60994.2024.10616067⟩. ⟨cea-04689662⟩
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Valentin Isaac Chassande, Adrian Evans, Yves Durand, Frédéric Rousseau. SpDCache: Region-Based Reduction Cache for Outer-Product Sparse Matrix Kernels. 35th IEEE International Conference on Application-specific Systems, Architectures and Processors, Jul 2024, Hong-Kong, Hong Kong SAR China. ⟨10.1109/ASAP61560.2024.00012⟩. ⟨cea-04676685⟩
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Léo de la Fuente, Jean-Frédéric Christmann, Manuel Pezzin, Matthias Remars, Olivier Sentieys. A Hardware Instruction Generation Mechanism for Energy-Efficient Computational Memories. IEEE International Symposium on Circuits and Systems, May 2024, Singapour, Singapore. ⟨10.1109/ISCAS58744.2024.10557870⟩. ⟨cea-04676665⟩
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Hugo Reymond, Abderaouf Nassim Amalou, Isabelle Puaut. WORTEX: Worst-Case Execution Time and Energy Estimation in Low-Power Microprocessors using Explainable ML. WCET 2024 - 22nd International Workshop on Worst-Case Execution Time Analysis, Thomas Carle, Jul 2024, Lille, France. pp.1:1-1:14, ⟨10.4230/OASIcs.WCET.2024.1⟩. ⟨hal-04646477⟩
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Notices
