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Mots clés

Loop PUF Power demand Robustness AES STT-MRAM Security and privacy GSM Estimation Reliability RSA Internet of Things Hardware security Asynchronous Computational modeling SoC Sécurité Variance-based Power Attack VPA Machine learning Formal proof Random access memory ASIC Power-constant logic Aging Countermeasures Countermeasure Circuit faults Reverse engineering Resistance FDSOI Electromagnetic Transistors Randomness Confusion coefficient Security Linearity Formal methods Convolution Process variation Energy consumption Elliptic curve cryptography Field Programmable Gates Array FPGA Dual-rail with Precharge Logic DPL Fault injection attack Information leakage Sensors Intrusion detection Logic gates DRAM Mutual Information Analysis MIA TRNG Protocols Masking Cryptography Side-channel analysis CRT Magnetic tunnel junction Routing Side-channel attacks Dynamic range Fault injection Tunneling magnetoresistance Filtering Differential power analysis DPA Magnetic tunneling Side-channel attacks SCA Lightweight cryptography SCA Side-channel attack OCaml Field programmable gate arrays Receivers Security services Switches Side-Channel Analysis Signal processing algorithms Spin transfer torque Application-specific VLSI designs Side-Channel Analysis SCA CPA Image processing Costs Temperature sensors Writing FPGA Defect modeling Authentication Reverse-engineering Side-Channel Attacks Differential Power Analysis DPA Coq MRAM 3G mobile communication PUF Hardware Simulation Training Neural networks Masking countermeasure Steadiness Voltage

 

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213

Références bibliographiques

428

Open access

39 %

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